Regviz

Silicon Labs /BGM240PB32VNN /EUSART1_NS /IEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IEN

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/EUSART1_NS/IEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXC)TXC 0 (TXFL)TXFL 0 (RXFL)RXFL 0 (RXFULL)RXFULL 0 (RXOF)RXOF 0 (RXUF)RXUF 0 (TXOF)TXOF 0 (TXUF)TXUF 0 (PERR)PERR 0 (FERR)FERR 0 (MPAF)MPAF 0 (LOADERR)LOADERR 0 (CCF)CCF 0 (TXIDLE)TXIDLE 0 (STARTF)STARTF 0 (SIGF)SIGF 0 (AUTOBAUDDONE)AUTOBAUDDONE 0 (RXTO)RXTO

Description

No Description

Fields

TXC

TX Complete Enable
TXFL

TX FIFO Level Enable
RXFL

RX FIFO Level Enable
RXFULL

RX FIFO Full Enable
RXOF

RX FIFO Overflow Enable
RXUF

RX FIFO Underflow Enable
TXOF

TX FIFO Overflow Enable
TXUF

TX FIFO Underflow Enable
PERR

Parity Error Enable
FERR

Framing Error Enable
MPAF

Multi-Processor Addr Frame Enable
LOADERR

Load Error Enable
CCF

Collision Check Fail Enable
TXIDLE

TX IDLE Enable
STARTF

Start Frame Enable
SIGF

Signal Frame Enable
AUTOBAUDDONE

Auto Baud Complete Enable
RXTO

RX Timeout Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data